Three principle sources of power supply perturbation exist within today's integrated circuits: resistive voltage (IR) drop; cyclic power supply ripple; and DI/DT induced supply bus ringing. IR drop is caused by the DC current demand of the Integrated Circuit (IC) and resistance of the power supply network within the IC and results in both reduced voltage at the operating circuits relative to the voltage supplied at IC level and voltage gradients across the IC. Cyclic power supply ripple is generated by clocked logic operating on the IC which creates periodic AC current variation and resultant voltage ripple. DI/DT induced supply bus ringing is caused by near-instantaneous current demand changes during IC power-up or when voltage island portions of the IC are enabled/disabled. These step response current changes excite the resistance/inductance/capacitance (RLC) network of the power supply bus generating a voltage ring that is damped over a transient time period which is much greater than the operational period (I/Operational Frequency) of the IC.
Current techniques for reducing DC/Ripple perturbation include quiet capacitance modeling and estimation, automatic power supply bus routing/generation and DC current modeling/load rebalancing. However, step response remains a serious problem in today's IC chips because voltage extremes produced during the step response dictate the minimum and maximum operating voltages encountered within an IC. In prior IC designs, the IC was powered up and down in total, and a wait time and reset performed after power bus stabilization to mitigate power-on transient response. Current IC designs increasingly provide voltage islands which are powered up and powered down multiple times while the remainder of the IC remains functional. A voltage island (VI) allows for one or more portions (islands) of an integrated circuit chip to be selectively powered by either a chip-wide power source or other voltage island power source. Voltage island power sources can be switched on and off in accordance with the operational demands of the integrated circuit requiring supply current from the chip-wide power source and consuming power only when required for functional operation of the IC.
However switching of the VI power supply places the IC at risk of failure due to step response voltage transients and their inherent oscillation frequencies. Each time an island is powered up, the initial current requirements needed to charge diffusions and wells within the island must come solely from on-chip quiet capacitors associated with the chip-wide power source, as the inductive properties of the package prevent real-time charge replacement. These sudden changes in current requirements generate a step response in the chip-package power bus network which results in damped ringing of the power bus voltage, i.e., power supply perturbation.
Referring to FIG. 6, circuit diagrams 500 of the T0− and T0+ power supply response due to voltage island power-on is shown. Just before power on, the bus system is stable and the quiet capacitance 504 in the circuit 502 is fully charged. The rate of change in current flow through the inductor 506 to Cq is 0. At time 0, voltage island capacitance, Cs 510, is switched onto the bus using switch 508 and begins to charge to the rail value. Charging of Cs 510 presents an instantaneous current demand in the circuit 502, or high di/dt to the VDD bus, however, due to the inductive component 506 of the bus, the initial di/dt current remains 0 and all charge pulled into Cs (510) is pulled out of Cq (504) in a charge sharing event. The result is that the voltage across Cq (Vcq) falls. The ratio of the Vcq at T0+ relative to Vcq at T0− illustrated in FIG. 6, is represented by the equation VDD′/VDD=Cq/(Cq+Cs) and is directly related to the capacitance of the voltage island relative to the IC remainder. Thus, an undesirable step response results which produces unwanted power supply perturbation.
The oscillation produced by the di/dt event excitement of the IC chip/package RLC network is typically in the 80 MHz to 200 MHz range in present day semiconductors. These frequencies are centered around clock frequencies typically encountered in ICs for both data processing and I/O functions which further compromises functionality of the IC as the voltage oscillation affects path delays within the IC from cycle to cycle. Past IC chip designs have been unable to adequately resolve the undesirable step response issue. With advances in IC technology and the drive to higher performance and lower power products, integrated circuits are being designed to lower rail voltages to power the chip. These challenges require even more attention to power distribution in the chip and the affects of step response perturbation at each new technology node.
Referring to FIG. 4, a typical known semiconductor IC module 300 including two voltage islands 310, 320 is shown. A power supply VDD is brought from off-module/chip from a plurality of VDD inputs 302 which are shorted together at chip level to form a robust power network/bus 308. Logic circuits, are distributed throughout the IC/chip 306 and attached to the power network. The two voltage islands 310, 320 are also powered by the power network 308, however, power to these islands of logic function 310, 320 is gated using header circuits 314, 322, respectively, disposed between the global power supply network of the IC chip/module 308 and the local power supply network of the voltage islands 310, 320. Each voltage island implemented within the IC/chip 306 may be controlled independently with regard to its power up/down condition at any time during IC function.
Referring to FIG. 5, the electrical equivalent of a typical IC RLC network 400 is shown. It is understood the logic functions connected to the power supply network consume some amount of functional current, and are modeled as capacitor components Cq 410 that comprise diffusions and wells within the circuits which provide storage capacity for charge associated with the power supply voltage VDD 404. As a result, circuits are modeled as the Cq component 410 of the power supply network. The summation of module, image and circuit contributions yields an RLC network 400 for the power bus. Similar to the logic outside voltage islands, logic inside a voltage island is modeled as a capacitance 422, however, as these supply capacitances are charged and discharged in response to a power supply switch (header) they are defined as switching capacitance (Cs) 422. The typical IC RLC network, as shown in FIG. 5, has disadvantages. For example, when power is brought in from off module/chip 402, and the voltage island switch 420 is engaged, unwanted inductance associated with the IC package and IC image is encountered. Additionally, while the power supply system within the IC is quite robust, there remains some amount of resistance associated with each segment of the bus 406 that affects both the transient and DC response of the power supply network.
Presently, noise reduction during voltage island turn on is managed through design of the header circuits which gate power to the voltage island. Headers are designed to provide a time-decreasing impedance between the power bus and island to slow charge up, and therefore reduce unwanted current step response (di/dt).
A block diagram for a prior art header circuit 550 is shown in FIG. 7. The header circuit 550 includes voltage supply VDD 560 and header control input 552 which provides selective coupling of voltage supply VDD 560 to Voltage Island Power Supply Rail 561 through a plurality of power supply coupling switches 554. Built-in delay units 556 time separate activation/deactivation switches 554 in response to control input 552 to limit di/dt during the voltage island power-up/power-down. In addition to header control input 552, typical voltage islands also include at least a second control signal to control the logic boundary of the VI independent of the header control 552. Design of these structures is complex and may not always optimize turn-on time for the internal capacitance of the voltage island. Thus, typical header circuits have not been successful in mitigating RLC-induced power supply ringing caused by current step response during voltage island power-up/power-down. Thus, there is a need for a circuit structure and method for coupling a voltage island to a semiconductor power bus which more effectively eliminates the step response and unwanted power supply perturbation of conventional IC designs.